1. Technical Field
The present invention generally relates to arithmetic operations in computer processors, and more particularly, to sharing overflow/underflow compare hardware to reduce power and circuit size requirements.
2. Description of Related Art
Currently, the arithmetic operations performance of many present processor implementations is increased by utilizing a floating-point processor. These floating-point processors can include overflow/underflow hardware, to determine if the exponent of a computed result creates an underflow or overflow condition.
Illustrated in FIG. 1A, is a block diagram representing an example of a prior art independent overflow circuitry 11. The exponent signal 5 is loaded into comparators 13 (A-N). Also loaded into comparators 13 (A-N) are a set of constants KO0-KON (12A-12N). These constants are architecture specific and related to the maximum exponent values. By comparing the exponent to these constant values, it is possible to determine if an overflow condition exists. The output of comparators 13 (A-N) is input into overflow logic 14.
Overflow logic 14 evaluates the output of comparators 13 (A-N) to determine whether or not the generation of an overflow signal is required. If the overflow logic 14 determines an overflow condition has occurred, the overflow logic 14 generates a high signal for the overflow signal 15. If overflow logic 14 determines that an overflow condition has not occurred, overflow logic 14 generates a low signal for the overflow signal 15.
Illustrated in FIG. 1B, is a block diagram representing an example of a prior art independent underflow circuitry 21. The exponent signal 5 is loaded into each comparator 23 (A-N). Also loaded into comparators 23 (A-N) are a set of constants KU0-KUN (22A-22N). These constants are architecture specific and related to the minimum exponent values. By comparing the exponent to these constant values, it is possible to determine if an underflow condition exists. The output of comparators 23 (A-N) is input into underflow logic 24.
Underflow logic 24 evaluates the output of comparators 23 (A-N), to determine whether or not the generation of an underflow signal is required. If the underflow logic 24 determines an underflow condition has occurred, the underflow logic 24 generates a high signal for the underflow signal 25. If underflow logic 24 determines that an underflow condition has not occurred, underflow logic 24 generates a low signal for the underflow signal 25.
A problem with the above described arrangement, is that the number of comparators used in the overflow/underflow circuitry increases dramatically with speculative compares. Speculative compares are used to compute many of the potential results absent some late arriving signals. The late arriving signals then select the correct operation results from the speculative compares. This further increases the size of the overflow/underflow comparison circuitry.
Another problem with the above described arrangement, is that some implementations may produce floating-point results of several different types of precision, requiring more comparisons to determine overflow/underflow conditions.
Illustrated in FIG. 2 is a block diagram representing an example of a prior art comparator circuitry 31. It is typical in floating point multiply-accumulate (FMAC) and in floating-point adder (FADD) implementations, that the normalized exponent to be off by 1 in the positive or negative. In these typical FMAC architectures, the exponent may be too large by 1 in the case where the leading bit anticipator (LBA) mispredicts the left shift amount necessary to normalize the mantissa. For cases where (C exp greater than AB exp), the addition of the AB mantissa to C mantissa may also create an overflow or underflow condition, requiring an addition of +1 or xe2x88x921, respectively, to the exponent.
As shown in FIG. 2, the AB exponent 32A and C exponent 32B signals are received by the comparator circuitry 31. The AB exponent 32A and C exponent 32B signals are input into the multiplexer 33A. Multiplexer 33A utilizes the greater than exponent selector 33B to select which exponent 32A or 32B is greater and input into adders 34A through 34C. The multiplexer 33A outputs the larger exponent of AB exponent 32A and C exponent 32B by selection of the greater than exponent selector 33B.
The output of multiplexer 33A is input into three (3) parallel adders 34 (A-C). Also input into the (3) parallel adders 34 (A-C) are the exponent shift amount 33C signal and the mantissa underflow possible 33D signal. The mantissa underflow possible signal 33D is connected to both a primary input and the carry input of adder 34C. Depending on whether the mantissa has the possibility of underflowing or overflowing, the exponent is potentially adjusted by 0 or 2. By adjusting the constants 36A and 36B by 1, the effective range of exponents that can be compared against is expxe2x88x921, exp, exp+1. The correct case generated by adders 34 (A-C) is selected by multiplexer 35A using the adjust amount select 35B. The resulting exponent then feeds into comparator circuitry 38 (A-D).
Overflow constants 36A and underflow constants 36B are input to multiplexers 37A and 37B respectively. Precision select signals 37C and 37D, select which constants from precision overflow constants 36A and precision underflow constants 36B are output by multiplexers 37A and 37B. The selected precision constants feed into comparator circuitry 38 (A-D). Outputs from comparator circuitry 33A-33D are compare results 39A-39D respectively. These compare results are used by overflow/underflow logic circuitry to compute the final overflow/underflow signals.
A problem with the above described arrangement is that the serialized adder and compare operations consume a large amount of time, and may not be fast enough for high performance FMAC or FADD implementations. Attempting to improve the performance of the compare circuitry 31 through speculative compares can dramatically increase the number of required comparators.
Thus, a heretofore unaddressed need exists in the industry to create a high-performance overflow/underflow comparator while reducing the number of comparators in an overflow/underflow current, thereby minimizing the complexity of the overflow/underflow comparison circuitry, reducing power consumption, and the time required to determine whether an overflow/underflow condition exists.
The present invention provides an apparatus and method for sharing overflow/underflow compare hardware in a FADD or FMAC unit to reduce power consumption and circuit size requirements.
Briefly described, in architecture, the overflow/underflow compare hardware sharing apparatus can be implemented as follows. Overflow/underflow possible check circuitry determines if a mathematical operation involving a first exponent signal and a second exponent signal creates a potential overflow condition. The overflow/underflow possible check circuitry generates a signal indicating if the overflow condition is a possibility. Exponent compare circuitry computes an actual overflow/underflow condition if the signal indicates overflow is possible. The exponent compare circuitry computes an actual underflow condition if the signal does not indicate overflow is possible.
The present invention can also be viewed as providing a method for sharing overflow/underflow compare hardware to reduce power and circuits size requirements. In this regard, the method can be broadly summarized by the following steps: (1) receiving a first exponent signal and a second exponent signal; (2) determining if a mathematical operation involving the first exponent signal and the second exponent signal creates a potential overflow condition; (3) generating a signal indicating if the potential overflow condition exists; (4) computing an actual overflow condition if the signal indicates the potential overflow condition exists; and (5) computing an actual underflow condition if the signal indicates the potential overflow condition does not exist.